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<title>EECS 141: Digital Integrated Circuits - Fall 1995</title>
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<center><h1><a name="867387"></a>EECS 141: Digital Integrated Circuits - Fall 1995</center></h1>

<!WA1><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867388"></a>This course aims to convey to the senior EECS students techniques to analyze and design digital integrated circuits. Upon completion of the course, the student will be able to design simple digital integrated circuits for a number of technologies (MOS and bipolar) and will be familiar with the use of modern Computer Aided Design Tools. As such he/she will be able to work in a team of designers.<p>

<h2>1. <a name="867393"></a>Contents</h2>

<!WA2><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867394"></a>The course will start with a detailed description and analysis of the core digital design block, being the inverter. Implementations in CMOS, ECL and BiCMOS design approaches will be discussed. Next the design of more complex combinational gates, such as NAND, NOR and EXORs, will be discussed, looking at optimizing the speed, area or power. The learned techniques will be applied on more evolved designs such as adders and multipliers. The influence of interconnect parasitics on the design performance and approaches to cope with them is treated. Substantial attention is devoted to the discussion of sequential circuits, clocking approaches and memories. The course will be concluded with a discussion of design methodologies. Significant emphasis is placed on the use of CAD Tools (SPICE and MAGIC) for homework, labs and projects.<p>

<h2>2. <a name="867395"></a>Prerequisites</h2>

<!WA3><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867396"></a>EECS 105 (ABSOLUTE REQUIREMENT!)<p>

<h2>3. <a name="867627"></a>Enrollment</h2>

<!WA4><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867628"></a>Due to classroom-size restrictions and constraints on the lab-equipment, the class enrollment is restricted to 76! The following priority scheme will be used when considering enrollment: 1) graduating seniors; 2) graduate students needing the class for prelim; 3) seniors; 4) juniors. If you don't need the class right away, please consider taking it later (as we are overenrolled at present).<p>

<h2>4. <a name="867409"></a>Course Material</h2>

<!WA5><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867410"></a>A new textbook is in preparation by Professor Rabaey titled "Digital Integrated Circuits: A Design Perspective." "Unfortunately, the actual book is only now going to press and will not be available until late fall. This text will be made available in the from of a reader from Copy Central on Euclid. Chapters 1-5 will be for sale at the end of the first week of class. Chapters 6 to 11 will be available midway through the semester.<p>

<h2>5. <a name="867417"></a>Assignments</h2>

<!WA6><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867455"></a>The weekly homework assignments will be handed out in class on Wednesday. They are due the next week before 5pm on Wednesday. They can be returned either in class or deposited in a special box, located in 558 Cory Hall, next to the desk of Corey Schaffer.<p>

<h2>6. <a name="867456"></a>Laboratories: S11 (Tu 3-6pm); S12 (Th 8-11am); S13 (We 11-2pm); S14(Th 3-6pm)</h2>

<!WA7><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867460"></a>The Laboratories are divided into Software Laboratories, to be performed on workstations, located in 111 Cory Hall and Hardware Laboratories, located in 353 Cory Hall. The software and hardware materials will be available from Copy Central the second week of class. The first lab is the second week of the semester and is on the MAGIC layout system.<p>

<h2>7. <a name="867669"></a>Discussion Sessions: Mo 4-5pm, Tu 3-4pm  both in 3107 Etcheverry Hall</h2>

<h2>8. <a name="867412"></a>Teaching Assistants</h2>

<b><a name="867413"></a>general e-mail: e141@po</b><p>

<b><a name="867448"></a>Teh-Wei Lee (tlee@cory) Office hours : Mo 2:30-4pm (469 Cory)</b><p>

<b><a name="867457"></a>Neil Bernstein (neilb@cory)  Office hours : Tu 1:30-3pm (469 Cory)</b><p>

<h2>9. <a name="867415"></a>Grades</h2>

<!WA8><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867398"></a>The course puts a considerable emphasis on the <i>design</i> aspect of the digital design process. This is reflected in the grading strategy for the course which uses the following weights:<p>

<b><a name="867399"></a>1. Homework Sets (about 12) 	  	 10%</b><p>

<b><a name="867401"></a>2. Design Projects (two) 	 20%</b><p>

<b><a name="867403"></a>3. Laboratory Projects (HW+CAD) 	 10%</b><p>

<b><a name="867404"></a>4. Midterms (2) 	 30%</b><p>

<b><a name="867405"></a>5. Final Exam 	 30%</b><p>

<h2>10. <a name="867418"></a>Detailed Schedule</h2>

10.1 <a name="867441"></a>Lectures<p>

<a name="867408"></a>Week 	  	 Topic 	  	 Reading in Rabaey<p>

<a name="867458"></a>1 	  	 Overview, Ideal Inverter, Devices, Static CMOS VTC 	 Ch 1, 2 & 3<p>

<a name="867397"></a>2 	  	 CMOS Propagation Delay and Layout Parasitics 	  	 Ch. 2 & 3, MAGIC Tools<p>

<a name="867459"></a>3 	  	 CMOS Gate Styles: Comp., DCVSL, Ratioed, Pass 	 Ch. 4 <p>

<a name="867443"></a>4 	  	 CMOS Gate Styles: Dynamic 	 Ch. 4<p>

<a name="867444"></a>5 	  	 CMOS Arithmetic Blocks (Midterm) 	 Ch. 5 (part)<p>

<a name="867439"></a>6 	  	 Bipolar Devices, Static VTC (Project 1 start) 	 Ch. 2 &3<p>

<a name="867462"></a>7 	  	 Bipolar Devices Propagation Delay 	 Ch. 2 &3<p>

<a name="867461"></a>8 	  	 Very High Speed Combinational Logic (Project 1 due) 	 Ch. 6<p>

<a name="867420"></a>9 	  	 Sequential Circuits 	 Ch. 8<p>

<a name="867442"></a>10  	  	 Sequential Circuits and Timing Issues (Midterm) 	 Ch. 8 & 9<p>

<a name="867445"></a>11 	  	 Coping with Interconnect  	  	 Ch. 7<p>

<a name="867430"></a>12 	  	 Coping with Interconnect (Project 2 start) 	  	 Ch. 7<p>

<a name="867440"></a>13 	  	 Memory and Array Structures 	 Ch. 10<p>

<a name="867463"></a>14 	  	 Memory and Array Structures (Project 2 due) 	 Ch. 10<p>

<a name="867464"></a>15 	  	 Design Methodologies 	 Ch. 11<p>

10.2 <a name="867400"></a>Labs:<p>

<b><a name="867414"></a>CAD 1 (Week 2): LAB2 (119 Cory Hall)</b><p>

<b><a name="867446"></a>CAD 2 (Week 3): LAB3 (119 Cory)</b><p>

<b><a name="867447"></a>CAD 3 (Week 4): LAB4 (119 Cory)</b><p>

<b><a name="867449"></a>CAD4 (Week 6): LAB5 (119 Cory)</b><p>

<b><a name="867453"></a>HW 1 (Week 9): CMOS Inverters (353 Cory)</b><p>

<b><a name="867451"></a>HW 2 (Week 11): BJT Inverters Switching Times (353 Cory)</b><p>

<b><a name="867452"></a>CAD 5 (Week 12): LAB 6 (119 Cory)</b><p>

<b><a name="867701"></a>HW 3 (Week 14): Static RAM (353 Cory)</b><p>

10.3 <a name="867411"></a>Projects<p>

<b><a name="867429"></a>PRJ 1 (Weeks 7&8) Design of an Arithmetic Building Block in CMOS</b><p>

<b><a name="867438"></a>PRJ 2 (Weeks 13&14) Design of a Sequential Circuit in CMOS</b><p>

10.4 <a name="867437"></a>Exams<p>

<!WA9><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867450"></a>Midterm 1 (Week 5): Fr. Sept. 29 (Material of Weeks 1-4<!WA10><img align=top src="http://infopad.eecs.berkeley.edu/icons/char/tiny_plus.gif">).<p>

<!WA11><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867454"></a>Midterm 2 (Week 10): Fr. Nov. 3 (Material of Weeks 5-9<!WA12><img align=top src="http://infopad.eecs.berkeley.edu/icons/char/tiny_plus.gif">).<p>

<!WA13><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867419"></a>Final (Exam Group 1): Mo Dec. 11, 8-11am (Material of Weeks 1-15)<p>

<h3><a name="867705"></a>Look in http://infopad.eecs.berkeley.edu/~icdesign for slides, software and other info related to the class.</h3>

<!WA14><img align=middle border=0 src="http://infopad.eecs.berkeley.edu/icons/char/indent.gif"><a name="867421"></a><p><center>  <!WA15><img align=middle src="http://infopad.eecs.berkeley.edu/~icdesign/FILES/figures/outline.fig_0.gif">  <p></center><p>

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